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AMD Xilinx
🇺🇸 United States·2024
Collected
HLSSemiconductor
Case Summary
Implemented a hardware-efficient field-programmable gate array (FPGA) implementation of a layered two-dimensional corrected normalized min-sum (2D-CNMS) decoder for quasi-cyclic low-density parity-check (QC-LDPC) codes in very small aperture terminal (VSAT) satellite communication systems.
Quantified Results
metric: 29–41 Mbps
Source
- Title
- A Novel FEC Implementation for VSAT Terminals Using High-Level Synthesis
- Type
- academic paper
- Year
- 2024
- Confidence Score
- 80%